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Valgrind 3.3 - Advanced Debugging and Profiling for GNU/Linux applications
by J. Seward, N. Nethercote, J. Weidendorfer and the Valgrind Development Team
Paperback (6"x9"), 164 pages
ISBN 0954612051
RRP £12.95 ($19.95)

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6.1.2 Cache simulation specifics

Cachegrind simulates a machine with independent first level instruction and data caches (I1 and D1), backed by a unified second level cache (L2). This configuration is used by almost all modern machines. Some old Cyrix CPUs had a unified I and D L1 cache, but they are ancient history now.

Specific characteristics of the simulation are as follows:

The cache configuration simulated (cache size, associativity and line size) is determined automagically using the CPUID instruction. If you have an old machine that (a) doesn't support the CPUID instruction, or (b) supports it in an early incarnation that doesn't give any cache information, then Cachegrind will fall back to using a default configuration (that of a model 3/4 Athlon). Cachegrind will tell you if this happens. You can manually specify one, two or all three levels (I1/D1/L2) of the cache from the command line using the ‘--I1’, ‘--D1’ and ‘--L2’ options.

On PowerPC platforms Cachegrind cannot automatically determine the cache configuration, so you will need to specify it with the ‘--I1’, ‘--D1’ and ‘--L2’ options.

Other noteworthy behaviour:

If you are interested in simulating a cache with different properties, it is not particularly hard to write your own cache simulator, or to modify the existing ones in ‘vg_cachesim_I1.c’, ‘vg_cachesim_D1.c’, ‘vg_cachesim_L2.c’ and ‘vg_cachesim_gen.c’. We'd be interested to hear from anyone who does.

ISBN 0954612051Valgrind 3.3 - Advanced Debugging and Profiling for GNU/Linux applicationsSee the print edition